1. Field of the Invention
The present invention is related to a signal relay circuit for relaying digital signals such as clock signals.
2. Description of the Related Art
As illustrated in FIG. 1, a prior art signal relay circuit comprises buffer IC (Integrated Circuit) 11 which receives a clock signal from driver IC 1, serving as a signal generating unit, through transmission line 10 and outputs the clock signal to receiver IC 7, serving as a signal receiving unit, through transmission line 12. The length of the transmission line for clock signal transmission is limited due to the driving capacity of driver IC 1. For this reason, in the case of the prior art signal relay circuit, buffer IC 11 is provided in the middle of the transmission line in order to extend the transmission distance of the clock signal.
Common mode noise is generated in such a structure having a buffer IC in the middle of a transmission line because of a through-current passed through the driver IC and the buffer IC. If common mode noise flows into an electric power source or a ground, then it is likely that the malfunction of another circuit or EMI (Electromagnetic Interference) will occur. Also, the costs required for implementing equipment such as a server system often increase by the use of such an expensive buffer IC.
Incidentally, Japanese Patent Laid-open Publication No. 170167/95 discloses a structure of a level shifter for AC signals for the purpose of eliminating self-exciting oscillation, comprising a capacitor and two resistors at the connection point between the capacitor and an inverter.